1. Field of the Invention
The invention pertains to lithographic processes for producing devices such as semiconductor devices.
2. Art Background
Lithographic processes play an important role in the manufacture of devices such as semiconductor devices. During the manufacture of such devices, a substrate is coated with an energy-sensitive material called a resist. Selected portions of the resist are exposed to a form of energy which induces a change in the solubility or reactivity of the exposed portions in relation to a given developing agent or etchant. By applying the developing agent or etchant to the resist, the more soluble or reactive portions of the resist are removed and portions of the substrate are bared. The bared portions of the substrate are then treated, e.g., etched or metallized.
Both organic and inorganic materials have been used as resists. The organic materials are typically organic polymers such as novolak resins which include quinone diazide sensitizers, while the inorganic materials are exemplified by chalcogenide glass-based materials such as germanium-selenium (Ge-Se) glass films supporting relatively thin layers of silver selenide (Ag.sub.2 Se). (Chalcogenide glass-based materials are materials which exhibit a noncrystalline structure and whose major constituent is sulfur, selenium, tellurium, or compounds thereof.) An organic polymer resist is typically spin-deposited onto a substrate. A Ge-Se glass film, on the other hand, is typically evaporated, e.g., e-beam evaporated or rf-sputtered, onto a substrate, and an Ag.sub.2 Se layer is formed on the surface of the Ge-Se glass film by dipping the film into an appropriate sensitizing bath.
The two types of resists, i.e., organic and inorganic resists, are useful in patterning essentially flat substrate surfaces, but difficulties arise when patterning nonplanar substrate surfaces, such as stepped substrate surfaces. For example, when an organic polymer resist (having a typical thickness of about 1-2 .mu.m) is spin-deposited onto a stepped surface having, for example, step heights greater than about 5 .mu.m, the resulting coating thickness is either discontinuous or substantially nonuniform, i.e., the coating sections covering the stepped portions of the surface are significantly thinner (typically more than about 50 percent thinner) than the coating sections covering the flat portions of the surface. Energy sufficient to ensure exposure of the thick resist sections causes overexposure of the thin sections. This overexposure results in a loss of linewidth control during pattern transfer into the substrate.
Attempts to overcome the difficulties associated with the patterning of stepped surfaces have involved the use of multilevel, e.g., bilevel, resists. For example, with bilevel resists, a relatively thin resist region is formed on a relatively thick, and thus planar, layer of an organic polymer (which need not be energy-sensitive) overlying a stepped surface. (In the case of, for example, the chalcogenide resists, a thick, planarizing layer is almost always deposited onto the substrate surface, regardless of whether it is stepped or flat, prior to deposition of the resist.) After exposure and development, the pattern defined in the resist is transferred into the planarizing layer by using the former as an etch mask during etching of the latter. Finally, the substrate is patterned by, for example, etching or metallizing the substrate surface through the patterned planarizing layer.
Bilevel resists (as well as other multilevel resists) are useful in patterning stepped surfaces where the step heights are less than about 5 .mu.m. However, while bilevel (and other multilevel) resists are still useful when patterning stepped surfaces having step heights greater than about 5 .mu.m, difficulties do arise. For example, the thickness of the planarizing layer covering a 5 .mu.m-step (in a surface having steps interspersed between flat portions) is often significantly less (typically more than about 50 percent less) than that covering the flat portions. Thus, when transferring a pattern to the planarizing layer using, for example, an isotropic etchant, the thin sections of the planarizing layer suffer excessive lateral etching during the additional time required to etch through the relatively thick sections. This excessive lateral etching results in a loss of linewidth control during pattern transfer into the substrate. Alternatively, if an anisotropic etching, e.g., reactive ion etching, technique is used, the additional time required to etch through the thickest portion of the planarizing layer causes pattern erosion of the overlying resist with a concomitant loss of linewidth control.
The difficulties associated with patterning nonplanar substrates have produced constraints on the fabrication of devices, e.g., semiconductor integrated circuit devices, having three-dimensional geometries, such as devices having components on the top, the bottom, or even on the sidewall, of a deep (deeper than about 5 .mu.m) V-groove or high (higher than about 5 .mu.m) step. Three-dimensional devices offer the possibility of increased packing densities using nominal design rules but, as discussed, techniques for patterning nonplanar substrates to achieve such devices have proven to be an elusive goal.